It is generally accepted that the use of high resistivity (or “HR”) semiconductor substrates of the silicon-on-insulator (“SOI”) type having a high concentration of interstitial oxygen (“High [Oi]” or “HiOi”) requires the use of heat treatments targeted at stabilizing the oxygen present in the silicon (e.g., by nucleation, precipitation, etc.) in order to render the substrate highly resistive.
In this context, “high resistivity” is understood to mean approximately 750Ω·m or more and “high concentration of interstitial oxygen” is understood to mean approximately 25 ppma or more, i.e., approximately 12.5×1017 atoms·cm−3 or more.
The abovementioned stabilization stage is conventionally carried out during the stage of sacrificial oxidation of the SOI following a layer transfer carried out, for example, by the known SMART CUT® technique. Conventionally, the stabilization stage is particularly carried out after a smoothing annealing subsequent to the layer transfer, which is generally a rapid annealing, i.e., RTA (“Rapid Thermal Anneal”). U.S. Patent Application Publication 2005/0026426 A1, titled “Method for Producing a High Quality Useful Layer on a Substrate,” published Feb. 3, 2005, the entire disclosure of which is incorporated by reference herein, discloses a stabilization stage subsequent to a stage of rapid annealing after the layer transfer.
On carrying out the electrical characterization of these materials (pseudo-MOS material), abnormally high interface state densities were demonstrated, typically reaching values of at least 20×1011 cm−2·eV−1, and resulting in a poor mobility of the carriers in the SOI, typically of approximately 400 cm2·V−1·s−1 or less for the electrons. Additional analyses (e.g., C-V characterization of an MOS capacitor) after removal of the SOI film and aluminium on a buried oxide contact have revealed fixed charge values in the buried oxide of at least 5×1010 cm−2 and crest interface state densities of at least 2×1011 cm−2·eV−1, thus showing that the source of this poor interface quality originated from the interface under the buried oxide.
One hypothesis put forward is that the smoothing annealing (RTA-type) results in modification of the distribution of unstabilized oxygen in the substrate, thus bringing about an increase in the amount of traps under the buried oxide.
One solution for overcoming this problem lies in the use of HR substrates having a very low concentration of interstitial oxygen (i.e., “Low [Oi]”), namely, below approximately 12 ppma, i.e., below approximately 6×1017 atoms·cm−3, which does not require stabilization annealing of the oxygen in the silicon (nucleation, precipitation). This is because this type of substrate is naturally highly resistive without having to carry out a specific treatment.
However, a disadvantage of the Low [Oi] HR substrates is very high sensitivity to the propagation of dislocations during heat treatments. For this reason, it is very difficult to obtain defect-free SOIs of the sliding-plane type using such substrates.
Consequently, an improvement in the quality of the High [Oi] HR substrates remains desirable. It is thus an objective of the present disclosure to provide a process for the manufacture of a high resistivity semiconductor substrate which makes it possible, in particular, for a substrate of the silicon-on-insulator type having a high concentration of interstitial oxygen, to obtain substrates of improved quality with respect to the known state of the art.
The abovementioned objective is achieved by a process for the manufacture of a high resistivity semiconductor structure by: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a buried oxide layer; and cleaving the compound substrate at the level of the weakened layer. In addition, the process includes at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the oxide layer before the stage of cleaving at the level of the weakened layer.
The prior art, as represented, in particular, by U.S. Patent Application Publication 2005/0026426 A1, previously incorporated by reference, teaches carrying out of a stabilization stage subsequent to a smoothing annealing stage, which is a stage occurring after cleaving the compound substrate at the level of the weakened layer. However, the prior art does not teach carrying out at least one stabilization stage before the smoothing annealing and, in particular, before the separation of the weakened layer.
Surprisingly, it has turned out that, by carrying out at least one heat treatment for stabilization of the interstitial oxygen in the silicon (e.g., nucleation, precipitation, growth of the precipitates) before the stage of cleaving at the level of the weakened layer, that is to say, before carrying out the smoothing annealing of the RTA-type, it is possible to improve the electrical (in particular, interfacial) properties of the resulting substrate, especially in the case of a high concentration of interstitial oxygen. Preferably, the at least one stabilization stage can thus be a stage of nucleation, precipitation and growth of the precipitates, in particular, a heat treatment comprising several stationary temperature phases.